iSES

Sridevan Parameswaran

Professor and Head

School of Electrical and Computer Engineering

The University of Sydney, Australia

Title

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Abstract

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Speaker Biography

Sri Parameswaran is a Professor and the Head of the School of Electrical and Computer Engineering at the University of Sydney. Prior this, he was a Professor in the School of Computer Science and Engineering at the Universtiy of New South Wales, and has also held the position of Acting Head of School at the School of Computer Science and Engineering at the University of New South Wales from 2019 to 2020. He has also served as the Program Director for Computer Engineering and Post Graduate Research Coordinator at the University of New South Wales, and was previously an academic at the University of Queensland. Sri Parameswaran has held visiting academic positions at Kyushu University in Japan and the University of California, Irvine, worked as a consultant at NEC Research Labs in Princeton and the Asian Development Bank, and served as a member of the Australian Research Council College of Experts. He is a Fellow of the IEEE.

Sri Parameswaran served as the Editor in Chief of the IEEE Embedded Systems Letters from 2016 to 2019. He was the General Chair of the IEEE/ACM International Conference on Computer-Aided Design (2017) and the Asia South Pacific Design Automation Conference (2012). He was an Executive Committee Member of the Design Automation Conference from 20212-2013. He serves or has served on the editorial boards of IEEE Transactions on Computer-Aided Design, ACM Transactions on Embedded Computing Systems, the EURASIP Journal on Embedded Systems, and the Design Automation of Embedded Systems. He has served on several Program Committees, such as ones at Design Automation Conference (DAC), Design and Test in Europe (DATE), the International Conference on Computer-Aided Design (ICCAD), the International Conference on Hardware/Software Code-sign and System Synthesis (CODES-ISSS), and the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES).

His research interests are Design Automation, System Level Synthesis, Low power systems, High-Level Synthesis, Computer architectures for bioinformatics, and Networks on Chips. Sri Parameswaran received his B.Eng degree from Monash University and his Ph.D. from The University of Queensland.

Satya Gupta

President

VLSI Society of India (VSI)

Bengaluru, India

Title

Title awaited

Abstract

Abstract awaited.

Speaker Biography

Dr. Satya Gupta is the President of the VLSI Society of India (VSI), where he provides leadership in advancing India's semiconductor ecosystem through industry, academia, government, and startup collaboration. A veteran semiconductor technologist, entrepreneur, and industry leader with more than three decades of experience, he has made significant contributions to VLSI design, ASIC development, semiconductor product engineering, and deep-tech innovation. He is widely recognized for his efforts in promoting indigenous semiconductor design, talent development, and technology entrepreneurship in India.

Throughout his distinguished career, Dr. Gupta has held several leadership positions across the global semiconductor industry. He has served as CEO of EPIC Foundation, Chairman of the India Electronics and Semiconductor Association (IESA), CEO of SenZopt Technologies, Founder and Vice President of Engineering at Open-Silicon, and led Concept2Silicon Systems before its acquisition by HCL Technologies. Earlier, he spent more than a decade at Intel, where he served as Director of ASIC Design and contributed to advanced semiconductor technologies and product development. His career spans multinational corporations, startups, industry organizations, and public policy initiatives focused on strengthening the electronics and semiconductor ecosystem.

Dr. Gupta is a frequent keynote speaker at leading international conferences and universities, where he advocates for innovation, semiconductor manufacturing, chip design, and workforce development. His current interests include VLSI design, ASICs, semiconductor product development, electronics manufacturing, AI hardware, entrepreneurship, and national semiconductor strategy. He is a strong proponent of building a globally competitive semiconductor ecosystem through research, education, startup incubation, and industry collaboration. Dr. Gupta holds a Ph.D. in High-Speed Computing, Massively Parallel Computing, and Neural Networks from Old Dominion University, an M.Tech. in Computer Engineering from IIT Delhi, and a B.E. in Electrical and Electronics Engineering from BITS Pilani.

Keshab K. Parhi

University of Minnesota Twin Cities

Minneapolis, MN USA

Title

Energy-Efficient Domain-Specific AI Models and Agents

Abstract

The field of artificial intelligence (AI) has taken a tight hold on broad aspects of society, industry, business, and governance in ways that dictate the prosperity and might of the world’s economies. The AI market size is projected to grow from $189 billion in 2023 to $4.8 trillion by 2033. Currently, AI is dominated by large language models (LLMs) that exhibit linguistic and visual intelligence. However, training these models requires a massive amount of data scraped from the web as well as large amounts of energy (50-60 GWh to train GPT-4). Despite these costs, these models often hallucinate, a characteristic that prevents them from being deployed in critical application domains. In contrast, the human brain consumes only 20W of power. What is needed is the next level of AI evolution in which lightweight domain-specific multimodal models with higher levels of intelligence can reason, plan, and make decisions in dynamic environments with real-time data and prior knowledge, while learning continuously and evolving in ways that enhance future decision-making capability. This will define the next wave of AI, progressing from today’s large models, trained with vast amounts of data, to nimble energy-efficient domain-specific agents that can reason and think in a world full of uncertainty. To support such agents, hardware will need to be reimagined to allow energy efficiencies ≥ 1000X over the state of the art. Such a vision of future AI systems is presented in this talk. The talk is based on collaborative work with colleagues as presented in arXiv 2510.22052.

Speaker Biography

Keshab K. Parhi received the B.Tech. degree from the Indian Institute of Technology (IIT), Kharagpur, in 1982, the M.S.E.E. degree from the University of Pennsylvania, Philadelphia, in 1984, and the Ph.D. degree from the University of California, Berkeley, in 1988. He has been with the University of Minnesota, Minneapolis, since 1988, where he is currently the Erwin A. Kelen Chair and a Distinguished McKnight University Professor in the Department of Electrical and Computer Engineering.

He has published over 750 papers, is the inventor of 36 patents, and has authored the textbook VLSI Digital Signal Processing Systems: Design and Implementation (Wiley, 1999). His current research addresses VLSI architecture design of artificial intelligence and machine learning systems, signal processing systems, hardware security, quantum information science, and data-driven neuroengineering and neuroscience with applications to neuro-psychiatric disorders.

Dr. Parhi is the recipient of numerous awards including the 2003 EEE Kiyo Tomiyasu Technical Field Award; and the 2017 Mac Van Valkenburg award, and the 2012 Charles A. Desoer Technical Achievement award, from the IEEE Circuits and Systems Society. He served as the Editor-in-Chief of the IEEE Trans. Circuits and Systems, Part-I during 2004 and 2005, and currently serves as the Editor-in-Chief of the IEEE Circuits and Systems Magazine. He is a Life Fellow of IEEE, a Fellow of the American Association for the Advancement of Science (AAAS), the Association for Computing Machinery (ACM), the American Institute of Medical and Biological Engineering (AIMBE), and the National Academy of Inventors (NAI).

Amit Patra

Director, IIT (BHU), Varanasi

Professor, IIT Kharagpur

Title

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Abstract

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Speaker Biography

Prof. Amit Patra, received the B.Tech., M.Tech. and Ph.D. degrees from the Indian Institute of Technology, Kharagpur in 1984, 1986 and 1990 respectively. During 1992-93 and in 2000 he visited the Ruhr-University, Bochum, Germany as a Post-doctoral Fellow of the Alexander von Humboldt Foundation. He joined the Department of Electrical Engineering, Indian Institute of Technology, Kharagpur in 1987 as a faculty member, and became a Professor in the Higher Academic Grade Pay in 2009. During 2018-19 he visited the University of Maryland, Baltimore County as a Senior Visiting Research Scientist and between 2019-22, he was recognized as an Honorary Adjunct Professor.

He was the Professor In-Charge, Advanced VLSI Design Lab, at IIT Kharagpur during 2004-07. Between 2007 and 2013 he served as the Dean (Alumni Affairs and International Relations) at IIT Kharagpur. Between 2013-15 he served in a voluntary role of the Executive Advisor, Institutional Development at IIT Kharagpur. From April, 2020 to December 2021, he was the Professor In- Charge, Rajarhat Research Park and from July, 2021 to May, 2024 he served as the Deputy Director of IIT Kharagpur. Currently, he is serving as the Director of IIT (BHU), Varanasi.

Nishit Gupta

Scientist 'E', Ministry of Electronics & Information Technology (MeitY), Government of India

Director (Design), India Semiconductor Mission

Title

Title awaited

Abstract

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Speaker Biography

Nishit Gupta is working as Scientist D in R&D in Electronics Group at Ministry of Electronics & information Technology, Government of India since 2014 wherein he is involved in broadening the Microelectronics research base across the country. He also holds an additional charge of Director (Technical) at India Semiconductor Mission setup under Digital India Corporation of MeitY for coordinating Semiconductor related activities for Government of India. Before joining MeitY, he has worked as Technical Leader in ‘Technology-R&D Group’ at ST Microelectronics for around a decade, wherein he was involved in developing and promoting System Level Methodologies around Transaction Level Modelling using SystemC, and SoC Architecture Analysis & Performance Evaluation at an early design phase. For his activities at MeitY, he primarily deals in evolving programmes and schemes to support domestic start-ups and academic in order to catalyse the fabless chip design ecosystem in the country.

Virendra Singh

Professor, Department of Electrical Engineering and Department of Computer Science & Engineering, Indian Institute of Technology Bombay

Title

Cyber Security, Computer Architecture, Processor Architecture & Micro-Architecture, Memory System Design, Reconfigurable Computing

Abstract

Abstract awaited.

Speaker Biography

Virendra Singh is currently a professor of Electrical and Computer Science at IIT Bombay. He received the B.E. and M.E. degrees in electronics and communication engineering from the Malaviya National Institute of Technology (MNIT), Jaipur, India, in 1994 and 1996, respectively, and the Ph.D. degree in computer science and engineering from the Nara Institute of Science and Technology (NAIST), Nara, Japan, in 2005.

Prior to joining IIT Bombay, he was a Faculty Member at the Supercomputer Education and Research Centre (SERC), Indian Institute of Science (IISc), Bengaluru, India, from 2007 to 2011. His research interests include high-performance computer architecture, testing and verification of high-performance processors, fault-tolerant computing, VLSI testing, design for test, formal verification of hardware designs, embedded system design, design for reliability, and CAD of VLSI Systems.

His research interests are in Cyber security, cyber physical systems, computer architecture, formal methods, VLSI testing and verification, Reinforcement Learning, adversarial learning, security of AI-based systems, blockchain technology, and hybrid quantum-HPC systems. He is an adjunct professor at various IITs and NITs.

Research Lab.: Computer Architecture and Dependable Systems Lab. (CADSL)
Coordinator: Indo-Japanese Joint Laboratory for Intelligent Dependable Cyber Physical Systems (IDCPS)
Coordinator: Information Security Research and Development Centre (ISRDC)
Associated Lab: Centre of excellence for Blockchain research
Affiliation: Centre for Machine Intelligence and Data Science

Vikram M. Gadre

Professor, Department of Electrical Engineering, Indian Institute of Technology Bombay

Title

Communication and signal processing, with emphasis on multiresolution and multirate signal processing, especially wavelets and filter banks: theory and applications

Abstract

Abstract awaited.

Speaker Biography

Vikram M. Gadre is a Professor in the Department of Electrical Engineering at the Indian Institute of Technology Bombay. He received his B.Tech. degree in Electrical Engineering from IIT Delhi in 1989, graduating with the President's Gold Medal, and his Ph.D. degree in Electrical Engineering from IIT Delhi in 1994.

He joined IIT Bombay as an Assistant Professor in July 1994, became an Associate Professor in February 2001, and has been serving as a Professor since March 2005. His research interests include communication and signal processing, with particular emphasis on multiresolution and multirate signal processing, wavelets, and filter banks, covering both theoretical foundations and practical applications.

His research and academic contributions span digital signal processing, wavelet-based methods, image and video processing, signal representation, and communication systems. He has been associated with the Texas Instruments Digital Signal Processing Laboratory at IIT Bombay and has contributed to research and educational initiatives in digital signal processing.

Prof. Gadre has received several academic honors, including the President's Gold Medal from IIT Delhi, the INAE Young Engineer Award, the IIT Bombay Research Paper Award, the S.S.I. Varshney Award, and multiple Excellence in Teaching awards from IIT Bombay. He has also contributed to engineering education through NPTEL courses on digital signal processing, multirate processing, and wavelets.