The iSES 2026 Preconference Tutorials will be held on 13–14 December 2026. The tutorial topics and speakers are listed below.
| Speaker and Designation | Tutorial Title |
|---|---|
|
Dr. Pramod Kumar Maurya
Scientist F, CSIR-National Institute of Oceanography (NIO), Goa |
Dynamics on Marine Robotics |
|
Shri Venkata Reddy Kolagatla
Scientist-D, Centre for Development of Advanced Computing (C-DAC), Bangalore Shri Mithun C Sriram (Co-presenter) C-DAC, Bangalore Shri Vivian Desalphine (Co-presenter) Scientist-F, C-DAC, Bangalore |
Efficient DFT Implementation for Modern VLSI SoCs - From JTAG / Boundary Scan and IJTAG to Scan Insertion, ATPG, Test Compression and Memory BIST |
|
Prof. Sujay Deb
Institute Chair Professor, Department of ECE & CSE, Indraprastha Institute of Information Technology (IIIT Delhi) |
Inserting Intrinsic PUF-Based Authentication Primitives in RISC-V and NoC-Based SoCs |
|
Prof. Virendra Singh
Professor, Department of Electrical Engineering and Department of Computer Science & Engineering, Indian Institute of Technology Bombay |
Cyber Security, Computer Architecture, Processor Architecture & Micro-Architecture, Memory System Design, Reconfigurable Computing |
|
Dr. Amit M. Joshi
Associate Professor, Department of Electronics and Communication Engineering, MNIT Jaipur |
Brain–Computer Interfaces for Smart Healthcare: Technologies, AI, and Emerging Applications |
Speaker
Scientist F, CSIR-National Institute of Oceanography (NIO), Goa
Lead Speaker
Scientist-D, Centre for Development of Advanced Computing (C-DAC), Bangalore
Venkata Reddy Kolagatla, a Scientist-D at C-DAC Bangalore, has six years of experience in cryptography, ASIC, and SoC design. He previously worked at Synopsys India and Sandisk India, specializing in SDR/DDR memory designs. A Gold Medalist in VLSI Systems from NIT Tiruchirappalli, he also holds a B.Tech in Electronics and Communication Engineering. At C-DAC, he led key ASIC projects and is recognized for his expertise in FPGA/ASIC design and cryptography, with numerous publications to his name.
Co-presenter
C-DAC, Bangalore
Co-presenter
Scientist-F, C-DAC, Bangalore
Vivian Desalphine is a Scientist-F at C-DAC Bangalore with around 19 years of experience. He is currently involved in the Chips-to-Startup Programme, Design Linked Incentive, and RISC-V GPU development. His work spans several national projects, including microprocessor development, cryptographic module validation, and high-performance network analysis tools. His expertise includes digital VLSI design, RISC-V microprocessor and GPU IP core development, secure microprocessor architectures, and SoC design. He holds a B.Tech in Electronics and Communications from the University of Kerala and a Master's in Digital Signal Processing from the University of Strathclyde, UK. He has numerous publications, a patent, and has contributed to industry technology transfers.
Speaker
Institute Chair Professor, Department of ECE & CSE, Indraprastha Institute of Information Technology (IIIT Delhi)
Prof. Sujay Deb is an Institute Chair Professor in the Department of Electronics and Communication Engineering and Computer Science and Engineering at Indraprastha Institute of Information Technology, Delhi. He received his PhD from the School of Electrical Engineering and Computer Science, Washington State University, Pullman, WA under the supervision of Dr. Partha Pratim Pande. His research Interests are broadly in the areas of power and performance efficient, secure and reliable System-on-Chip Design, Network-on-Chip (NoC) communication fabrics, Heterogeneous System Architectures (HSA), hardware for deep learning, low cost bio-sensors for preventive healthcare. More specifically, topics of interest include: intra and inter-chip wireless interconnection, efficient and reliable routing schemes, scalable coherence protocols for many-core systems, hardware support for on-chip broadcast and multi-cast traffic, cache architectures for HSA, single chip bio potential acquisition system for preventive health-care. He also works on application of technology to chiplet architectures, healthcare, hardware security, mobile sensing etc. He is currently serving as IEEE CASS CSS Delhi section Vice Chairman. He is a senior member of IEEE.
Speaker
Professor, Department of Electrical Engineering and Department of Computer Science & Engineering, Indian Institute of Technology Bombay
Virendra Singh is currently a professor of Electrical and Computer Science at IIT Bombay. He received the B.E. and M.E. degrees in electronics and communication engineering from the Malaviya National Institute of Technology (MNIT), Jaipur, India, in 1994 and 1996, respectively, and the Ph.D. degree in computer science and engineering from the Nara Institute of Science and Technology (NAIST), Nara, Japan, in 2005. Prior to joining IIT Bombay, he was a Faculty Member at the Supercomputer Education and Research Centre (SERC), Indian Institute of Science (IISc), Bengaluru, India, from 2007 to 2011. His research interests include high-performance computer architecture, testing and verification of high-performance processors, fault-tolerant computing, VLSI testing, design for test, formal verification of hardware designs, embedded system design, design for reliability, and CAD of VLSI Systems. His research interests are in Cyber security, cyber physical systems, computer architecture, formal methods, VLSI testing and verification, Reinforcement Learning, adversarial learning, security of AI-based systems, blockchain technology, and hybrid quantum-HPC systems. He is an adjunct professor at various IITs and NITs. Research Lab.: Computer Architecture and Dependable Systems Lab. (CADSL) Coordinator: Indo-Japanese Joint Laboratory for Intelligent Dependable Cyber Physical Systems (IDCPS) Coordinator: Information Security Research and Development Centre (ISRDC) Associated Lab: Centre of excellence for Blockchain research Affiliation: Centre for Machine Intelligence and Data Science
Speaker
Associate Professor, Department of Electronics and Communication Engineering, MNIT Jaipur
Dr. Amit M. Joshi completed his M.Tech and Ph.D. from SVNIT, Surat in 2009 and 2015 respectively. He is currently an Assistant Professor at Malaviya National Institute of Technology, Jaipur (MNIT Jaipur) since July 2013. His area of specialization is Biomedical signal processing, Smart healthcare, VLSI DSP Systems, and embedded system design. He is a senior member of IEEE, member of IETE, and member of IEEE. He has also published 90+ research articles in excellent peer-reviewed international journals/conferences and also has published six book chapters. He has a total of 2449 google scholar citations, i10 index 67, H-index 27. He served as a reviewer of technical journals such as IEEE Transactions/ IEEE Access, Springer, and Elsevier and also served as a Technical Programme Committee member for IEEE conferences (iSES, ICCE, ISVLSI, VDAT). He also received the honour of UGC Travel fellowship, the award of SERB DST Travel grant, and CSIR fellowship and also attended well known IEEE Conferences TENCON-16, TENCON-17, ISCAS-18, MENACOMM-19, etc across the world. He has also served as Mentor for IEEE Engineering in Medicine and Biology Society student mentorship program 2021. He has supervised 8 PhD theses, and five more research scholars are working under his supervision. He supervised 23 M.Tech projects and 17 B.Tech projects in Biomedical Signal Processing, VLSI/Embedded Systems. He is also the founder and Director of the startup - Svaarogyam Medical Devices Pvt. Ltd. at MIIC.
